Power Integrity in High Speed Digital FPGA Board

As the speed of the data signal increases, many reasons including power supply noise lead to the degradation of the high-speed signals. In low power high-speed digital interfaces, it is crucial to characterize the whole system power supply in order to minimize power supply noise in the system. High-speed design failures show up as failures at higher operating frequency, data error rates, cross talk errors, and EMI errors. The debugging of high-speed related errors may need expensive instruments, e.g. high bandwidth oscilloscope, spectrum analyzers, time domain reflectometer, to detect and understand the failure mechanism. Currently, PI engineers do Power Integrity (PI) analysis of power system to ensure proper and reliable operation using Electronic Design Automation tools (EDA) before the actual fabrication of board. This reduces board failure chances significantly and also cuts production time.
Signal integrity (SI) and PI are two distinct but related realms of analysis concerned with the proper operation of digital circuits. In SI, the main concern is to make sure that transmitted 1s looks like 1s at the receiver (and same for the 0s). In PI, the main concern is to ensure that the drivers and receivers are provided with adequate current to send and receive 1s and 0s. SI and PI analyzes concerned with the proper analog operation of digital circuits, therefore; care must be taken at the design stage itself to ensure that the design is in accordance with high-speed design rules.

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