High Definition Multimedia Interface (HDMI) has become very popular digital interfaces in the consumer electronics arena for high definition video and audio with personal computers and in-home theatre systems. The HDMI signal is transmitted from the video player (source) to the LCD panel (sink). As the panel size growing larger, and the display resolution growing higher as 4K2K, the required maximum data rate of HDMI reaches 3.4 Gbps. HDMI is a high-speed, serial digital signaling system that is designed to transport extremely large amounts of digital data over a long cable length with very high accuracy and reliability.
SERDES is a high-speed serial data link used in integrated circuits (ICs) to serialize the parallel data and transfer it at a much faster rate. A typical SERDES architecture looks like a communication set-up with a transmit and a receive side. At transmit side, a PLL generates the fast clock necessary to drive the serializer. A clock and data recovery (CDR) circuit recovers a clock from the transmitted serial data and retimes the data at the receive side. One advantage of using SERDES is reduced clock skew, so data can be sent at the GHz rate. The main disadvantage in SERDES is timing jitter, the deviation of the actual signal transition from the expected transition in time. Timing skew is not a problem in serial interface because in each data lane, there is only one differential signal in each direction, and there is no external clock signal since clocking information is embedded within the serial signal itself.
With increased data rates of high-speed input/output I/O buses, maintaining the signal quality of the transmission channel becomes challenging due to parasitic effects from interconnects which did not impact the overall performance at lower data rates. Over the past decade, data rates for electrical interconnects have experienced a dramatic increased to meet ever increasing demands of more I/O bandwidth from modern networking applications and high-capacity storage