SATA Connector : High Speed Interconnect signal Integrity Analysis

The introduction of SATA 6 Gb/s promises new levels of performance for networks. At these higher speeds, signal integrity becomes a significantly more important design concern for equipment designers and network engineers than for SATA 3 Gb/s architectures, as tolerances drop to the point where test equipment can adversely affect signal integrity. For example, a test setup that was operating at the performance edge for 3 Gb/s will cause undesirable and misleading failures at the 6 Gb/s speed.

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Interconnect is the complete path that connects one device (e.g. CPU, chipset, memory…) to another. Maintaining good signal quality throughout high-density and high-speed interconnects is crucial due to ever-increasing demands for cleaner signal transmission. The requirement of a new high-speed multi pin connector is to enable a data transmission at very high rate (~ 5Gbit/s) in various systems. In this application high speed SATA interconnects connectors is characterized with ADS and EMPro simulation tools.

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Design and simulation

High-speed connector SATA is designed and simulated using EMPro using Finite Element Method (FEM) solver. This connector is imported in ADS as a library component using ADS-EMPro interoperability feature.   Finally, three different post layout Signal Integrity (SI) analysis is carried out in ADS schematic window to validate waveform quality, timing, and crosstalk.

  1. Channel analysis, with a single TX_Diff component and no crosstalk effect
  2. RF Board Traces Channel analysis with a single TX_Diff component and crosstalk effect
  3. Channel analysis with a single TX_Diff component and 8B10B encodingsata5 The results are obtained for integrated system over a frequency range from 0 to 5 GHz. Eye diagram and Bathtub curves are optimized at data transmission rate of 5Gbit/s using decaps. The complex problem of Signal Integrity is solved with integration of system, circuit, and EM (electromagnetic) simulators that reduced design cycle time and provide accurate answers. Presented technique in this paper can be leverage by other SI analysis of systems.

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