Compliance Test of PCIe Gen3 Serial Channel

With increased data rates of high-speed input/output I/O buses, maintaining the signal quality of the transmission channel becomes challenging due to parasitic effects from interconnects which did not impact the overall performance at lower data rates. Over the past decade, data rates for electrical interconnects have experienced a dramatic increase from 1 GB/s to 25 GB/s and beyond to meet ever increasing demands of more I/O bandwidth from modern networking applications and high-capacity storage.

SERDES is a high-speed serial data link used in integrated circuits (ICs) to serialize the parallel data and transfer it at a much faster rate. A typical SERDES architecture looks like a communication set-up with a transmit and a receive side. At transmit side, a PLL generates the fast clock necessary to drive the serializer. A clock and data recovery (CDR) circuit recovers a clock from the transmitted serial data and retimes the data at the receive side. One advantage of using SERDES is reduced clock skew, so data can be sent at the GHz rate. The main disadvantage in SERDES is timing jitter, the deviation of the actual signal transition from the expected transition in time. Timing skew is not a problem in serial interface because in each data lane, there is only one differential signal in each direction, and there is no external clock signal since clocking information is embedded within the serial signal itself.

PCI Express (PCIe) is one example of serial interconnects. The development of PC Express was driven by the need for much greater performance. PCI Express using high speed, 8Gbit/s serial links can suffer from a large array of physical phenomena including crosstalk, impedance discontinuities resulting in reflections (causing jitter), intersymbol interference, and mode conversion due to unbalanced transmission lines can lead to excessive EMI emissions in a large system. Signal Integrity Analysis and compliance testing is carried out to ensure high signal quality.

PCI Express Gen3 (PCIe 3.0) Interface

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PCI Express is the next generation Peripheral Component Interconnect (PCI) standard. The third generation, PCI Express Gen3, is a high speed differential I/O interconnects that runs at 8.0 Gigabits/second, it is widely used in computers and servers. Fig. 1 shows a typical PCIe Gen3 link, the channel could be short and straightforward with only a few inches of interconnect between the driver and the receiver, or could be long and complicated. The PCIe 3.0 channel can consist of anywhere from one to 32 lanes. The PCIe standard defines connectors for multiple widths: x1, x4, x8, x12, x16 and x32, where x represents lane.

PCI Interface Simulation Methodology   

Performing a circuit simulation on a high-speed serial interface requires circuit models of the transmitter (TX) and receiver (RX), transmission line models of the die, package, PCB traces, vias and connectors that interconnect the elements. A time domain based circuit simulator combines these model elements, supplies a pseudo-random bit sequence (PRBS) stimulus to excite the current and voltage waveforms and Eye probes to observe the response. The passive components of the link are collectively called the channel. To ensure high quality signal, it is important to carefully design all aspects of these passive channel interconnects.

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DesignCon Paper Listing

Presented this paper in DesignCon 2017 at Santa Clara

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One response to “Compliance Test of PCIe Gen3 Serial Channel

  1. Pingback: PCIe 3.0 Connector EM Simulation for SI Analysis | Anil Kumar Pandey·

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