PCI Express (PCIe) is one example of serial interconnects. The development of PC Express was driven by the need for much greater performance. The PCI Express standard defines slots and connectors for multiple widths: ×1, ×4, ×8, ×12, ×16 and ×32. A 32-lane PCIe connector (×32) can support an aggregate throughput of up to 16 GB/s. The width of a PCIe connector is 8.8 mm, while the height is 11.25 mm, and the length is variable. The fixed section of the connector is 11.65 mm in length and contains two rows of 11 (22 pins total), while the length of the other section is variable depending on the number of lanes. The pins are spaced at 1 mm intervals, and the thickness of the card going into the connector is 1.8 mm. For Signal Integrity analysis and compliance testing of complete PCIe channel, it’s important to include connector model in channel simulation.
High-speed PCIe connector is designed and simulated using Finite Element method (FEM). From this analysis, important factors from a Signal Integrity point of view (e.g., impedance matching, reflection, attenuation, impedance mismatch, propagating delay, crosstalk, and alignment shapes of connectors) are analyzed. In order to minimize impedance effects, the connector contact geometry is designed to keep the impedance profile as flat as possible. Above fig displays the 3D model and pin configuration of the PCIe connector. 32 pins are used as 16 pair of differential signals for 8 lanes. Simulated return loss is shown below in fig. The return loss is better than -9 dB while the insertion loss is less than -1.5 dB over the band (0-8 GHz).
This simulated data is used for signal integrity analysis of complete channel of PCIe 3.0.
Reference : COMPLIANCE TEST OF PCIE GEN3 SERIAL CHANNEL