The increased data rates of today’s high-speed Input/ Output (I/O) buses make maintaining transmission channel signal quality all the more challenging. One reason for the challenge is the parasitic effects that result from bus interconnects. Over the past decade, data rates for electrical interconnects have experienced a dramatic increase—from 1 Gbps to 25 Gbps and beyond—to meet the ever increasing demand for more I/O bandwidth from modern networking applications and high-capacity storage.
Enter the Serializer/De-serializer (SerDes), a high-speed serial data link used in ICs to serialize parallel data and transfer it at a much faster rate. Today, Gigahertz SERDES is a leading inter-chip and inter-board data transmission technique for high-end computing devices. PCI Express (PCIe) is a high-speed serial interconnect protocol conceived as a way to overcome many of the limitations in conventional parallel buses, address ever increasing bandwidth requirements and provide much greater performance. It does so by providing a scalable, point-to-point serial connection between chips, while maintaining compatibility with conventional PCI at the software layer. While this bodes well for designers, it also creates a host of challenges, which make signal integrity analysis and compliance testing absolutely essential to ensuring high signal quality.
The Challenge: PCIe 3.0 Interface
PCIe is a standard maintained and developed by the PCI Special Interest Group (PCI-SIG), a community of companies responsible for developing and maintaining the standardized approach to peripheral component I/O data transfers. The third-generation of the PCIe standard, PCI Express Gen3 (PCIe Gen3), specifies a high-speed differential I/O interconnect that runs at 8.0 Gbps. It is widely used in computers and servers.
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- Signal Integrity Journal
- Test and Measurement Journal
- Design Con 2017 Paper by Anil Pandey
- Google Scholar -Anil
- Keysight Blog