Signal and Power Integrity Analysis of DDR4 Address Bus

In this paper, a unique technical approach is presented to accurately analyze and optimize the address bus of an onboard DDR4 memory module by taking power plane induced noise and thermal effect simultaneously in the analysis. For high-speed digital designers, designing data channel in DDR4 memory is always challenging due to high data rates of 3.2GB/s per data signal at a low-voltage of 1.2V. The design is simulated at 1.6 Gbps that is the highest DDR4 switching rate in a configuration containing four memory devices. It is important to catch SI and PI problems at an early stage in design that requires fast and accurate signal integrity analysis for address bus. To maximize eye opening, address bus interconnects impedance optimization is carried out. DDR4 power plane and address signals are analyzed using PI-SI solver that is based on full-wave electromagnetic simulation, then the transient simulation is performed on combined PI data of power plane and address bus. The coupling of simultaneous switching noise (SSN), power plane jitter and thermal effects on DDR4 address bus signals are accounted in power and thermal-aware signal integrity analysis using PIPro signal integrity solution.


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