Power-Aware signal integrity analysis of DDR4 data bus is necessary for the channel reliability and robustness. In high- speed digital (HSD) boards due to simulation tools limitation, power integrity, and signal integrity analysis are performed separately. The complete data channel performance is the cumulative effect of whole interconnect environment that consists of transceiver ICs, power planes, bond wires, board substrate, data lines and board interconnects that’s why it’s necessary to consider power plane generated noise effect in data channel signal integrity analysis.
In high-speed digital boards, to reduce the parasitic of the power supply, as well as to increase high-frequency decoupling several power and ground planes are placed in an alternating manner. Data signal lines are routed between these plane pairs. At high-speed it’s crucial to characterize both power delivery network and data bus and accurately account the power supply induced jitter to minimize power supply noise in the system. Mainly high-speed design failures are data error rates, cross talk errors, power plane noise coupling to signal causing errors and EMI errors. SI engineers do power-aware SI analysis of channel to ensure proper and reliable operation using Electronic Design Automation tools (EDA) before actual fabrication of board. This reduces board failure chances significantly and also cut production time.
In signal integrity, the main objective is to make sure that transmitted 1s and 0s look like same at the receiver. In power integrity, the main objective is to make sure that the ICs are provided with suitable current to send and receive 1s and 0s. In DDR4 signaling is single ended like DDR3 but data lines have moved closer towards point-to-point interconnect and the interface on the controller side. On the power design front, DDR4 systems use very-low-voltage signaling (1.2V).
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- Anil Pandey : Google Scholar
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- Power Integrity Analysis of Power Delivery System in High Speed Digital FPGA Board